With the shrinking sizes of hardware devices, design susceptibility to soft errors became a significant concern in electrical designs. Most modern designs, from ASICs to microprocessors, contain some degree of Error Detection and/or Correction (EDC) capabilities, often implemented as additional logic. In some cases, a design may adhere to very strict reliability requirements and may be designed with an extensive amount of EDC in it such that almost all functional latches may be protected against soft (or hard) errors using hardware error checkers.
Different methodologies and techniques are used in order to verify that a given design meets its reliability requirements. One of these methods is code reviews, which occurs during the logic implementation phase. The goal of the review process is to make sure that latches in the design are protected according the corresponding specification. For example, if a command bus is specified to be protected by parity checking, the design reviewer will have to make sure that is what was actually implemented in the hardware description (e.g., VHDL files). As this process involves going thru many lines of code in many files, it is very time-consuming and error-prone.